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fn7100 rev 5.00 page 1 of 17 march 9, 2006 fn7100 rev 5.00 march 9, 2006 el7581 3-channel dc/dc converter datasheet the el7581 is a 3-c hannel dc/dc converter ic which is designed primarily for use in tft/lcd applications. it features a pwm boost converte r with 2.7v to 14v input capability and 5v to 17v outpu t, which powers the column drivers and provide s up to 720ma @12v, 570ma @ 15v from 5v input. a pair of charge pump control circuits provide regulated outputs of v on and v off supplies at 8v to 40v and -5v to -40v, respective ly, each at up to 60ma. the el7581 features adjusta ble switching frequency, adjustable soft start, and a separate output v on enable control to allow selection o f supply start-up sequence. an over-temperature feature is p rovided to allow the ic to be automatically protected from excessive power dissipation. the el7581 is available in a 20 ld htssop package and is specified for oper ation over the full -40c to +85c temperature range. features ? tft/lcd display supply - boost regulator -v on charge pump -v off charge pump ? 2.7v to 14v v in supply ?5v < v boost < 17v ?5v < v on < 40v ? -40v < v off < 0v ?v boost = 12v @ 720ma ?v boost = 15v @ 570ma ? high frequency, small indu ctor dc/dc boost circuit ? over 90% efficient dc/dc boost converter capability ? adjustable frequency ? adjustable soft-start ? adjustable outputs ? small parts count ? pb-free plus anneal available (rohs compliant) applications ? tft-lcd panels ?pdas pinout el7581 (20 ld htssop) top view ordering information part number part marking tape & reel package pkg. dwg. # el7581ire 7581ire - 20 ld htssop mdp0048 el7581ire-t7 7581ire 7 20 ld htssop mdp0048 EL7581IRE-T13 7581ire 13 20 ld htssop mdp0048 el7581irez (note) 7581irez - 20 ld htssop (pb-free) mdp0048 el7581irez-t7 (note) 7581irez 7 20 ld htssop (pb-free) mdp0048 el7581irez-t13 (note) 7581irez 13 20 ld htssop (pb-free) mdp0048 note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds/d ie attach materials and 100% matte tin plate termination finish, which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free products are msl clas sified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. thermal pad* rosc enp enbn vref pgnd pgnd drvp vddp fbp vssp vssb ss fbb vddb lx lx lx drvn vddn fbn *refer to pcb layout guideline. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 n o t r e c o m m e n d e d f o r n e w d e s i g n s n o r e c o m m e n d e d r e p l a c e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e r s i l o r w w w . i n t e r s i l . c o m / t s c
el7581 fn7100 rev 5.00 page 2 of 17 march 9, 2006 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maximum ratings (t a = 25c) v in input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14v v ddb , v ddp , v ddn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18v lx voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18v maximum continuous output current . . . . . . . . . . . . . . . . . . . . . .1a storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c die junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves operating ambient temperature . . . . . . . . . . . . . . . .-4 0c to +85c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. electrical specifications v in = 3.3v, v boost = 12v, r osc = 100k ? , t a = 25c unless otherwise specified. parameter description conditions min typ max unit dc/dc boost converter iq1_b quiescent current - shut-down enbn = enp = 0v 0.8 10 a iq2_b quiescent current - switching enbn = v ddb 4.8 8 ma v(fbb) feedback voltage 1.275 1.300 1.325 v v ref reference voltage 1.260 1.310 1.360 v v rosc oscillator set voltage 1.260 1.325 1.390 v i(fbb) feedback input bias current 0.1 a v ddb boost converter supply range 2.7 17 v d max maximum duty cycle 85 92 % i(lx) max peak internal fet current 2.75 a r ds-on switch on resistance at v boost = 10v, i(lx) total = 500ma 0.15 ? i leak-switch switch leakage current i(lx) total 2 a v boost output range v boost > v in + v diode 517v ? v boost / ? v in line regulation 2.7v < v in < 13.2v, v boost = 15v 0.1 % ? v boost / ? i o1 load regulation 50ma < i o1 < 300ma 0.5 % f osc-range frequency range r osc range = 240k ? to 60k ? 200 1000 khz f osc1 switching frequency r osc = 100k ? 620 680 750 khz positive regulated charge pump (v on ) most positive v on output depends on the magnitude of the v ddp input voltage (normally connected to v boost ) and the external component configuration (doubler or tripler) v ddp supply input for positive char ge pump usually connected to v boost output 5 17 v iq1(v ddp ) quiescent current - shut-down enp = 0v 11.5 20 a iq2(v ddp ) quiescent current - switching enbn = enp = v ddb 2.35ma v(fbp) feedback reference voltage 1.245 1.310 1.375 v i(fbp) feedback input bias current 0.1 a i(drvp) rms drvp output current v ddp = 12v 60 ma v ddp = 6v 15 ma ilr_v on load regulation 5ma < i l < 15ma -0.5 0.03 0.5 %/ma f pump charge pump frequency frequency set by r osc - see boost section 0.5*f osc
el7581 fn7100 rev 5.00 page 3 of 17 march 9, 2006 negative regulated charge pump (v off ) most negative v off output depends on the magnitude of the v ddn input voltage (normally connected to v boost ) and the external component configuration (doubler or tripler) v ddn supply input for negative char ge pump usually connected to v boost output 5 17 v iq1(v ddn ) quiescent current - shut-down enbn = 0v 1.2 10 a iq2(v ddn ) quiescent current - switching enbn = v ddb 2.3 5 ma v(fbn) feedback reference voltage -80 0 +80 mv i(fbn) feedback input bias current magnitude of input bias 0.1 a i(drvn) rms drvn output current v ddn = 12v 60 ma v ddn = 6v 15 ma ilr_v off load regulation -15ma < i l < -5ma -0.5 0.03 0.5 %/ma f pump charge pump frequency frequency set by r osc - see boost section 0.5*f osc enable control logic v hi-enx enable input high threshold x = bn, p 1.4 v v lo-enx enable input low threshold x = bn, p 0.6 v il(enx) logic low bias cu rrent x = bn, p = 0v 0.1 a il(enbn) logic high bias current enbn = 5v 7.5 15 a il(enp) logic high bias current enp = 5v 3.3 7.5 a over-temperature protection t ot over-temperature threshold 130 c t hys over-temperature hysteresis 40 c electrical specifications v in = 3.3v, v boost = 12v, r osc = 100k ? , t a = 25c unless otherwise specified. (continued) parameter description conditions min typ max unit
el7581 fn7100 rev 5.00 page 4 of 17 march 9, 2006 pin descriptions i = input, o = output, s = supply pin number pin name pin type pin function 1 vssb s ground for dc/dc boost and re ference circuits; chip subst rate 2 ss i soft-start input; the capacitor connected to this pin sets the current limited start time 3 fbb i voltage feedback input for boost circuit; det ermines boost output voltage, v boost 4 vddb s positive supply inpu t for dc/dc boost circuits 5 lx o boost regulator inductor driv e connected to drain of intern al nfet 6 lx o boost regulator inductor driv e connected to drain of intern al nfet 7 lx o boost regulator inductor driv e connected to drain of intern al nfet 8 drvn o driver output for the external generation of negative cha rge pump voltage, v off 9 vddn s positive supply for input for v off generator 10 fbn i voltage feedback input to determine negative charge pump output, v off 11 vssp s negative supply pin for both the positive and negative c harge pumps 12 fbp i voltage feedback to determine positive charge pump output , v on 13 vddp s positive supply input for v on generator 14 drvp o voltage driver output for the external generation of pos itive charge pump, v on 15 pgnd o power ground, connected to source of internal nfet 16 pgnd o power ground, connected to source of internal nfet 17 vref i voltage reference for charge pump circuits; decouple to ground 18 enbn i enable pin for boost (v boost generation) and negative charge pump (v off generation); active high 19 enp i enable for drvp (v on generation); active high 20 rosc i connected to an external resistor to ground; sets the sw itching frequency of the dc/dc boost
el7581 fn7100 rev 5.00 page 5 of 17 march 9, 2006 typical performance curves figure 1. efficiency vs i out figure 2. efficiency vs i out figure 3. efficiency vs i out figure 4. efficiency vs i out figure 5. load regulation figure 6. load regulation 95 90 85 80 75 70 65 60 0 200 400 600 800 1k i out (ma) efficiency (%) v in = 5v f s = 1mhz 15v 9v 12v 95 90 85 80 75 70 65 60 0 200 400 600 800 1k i out (ma) efficiency (%) v in = 3.3v f s = 700khz 15v 5v 9v 12v 95 90 85 80 75 70 65 60 0 200 400 600 800 1k i out (ma) efficiency (%) 15v 9v 12v v in = 5v f s = 700khz 95 90 85 80 75 70 65 60 0 200 400 600 800 1k i out (ma) efficiency (%) v in = 3.3v f s = 1mhz 15v 9v 12v 5v 2 1.5 1 0 -1 -1.5 -2 50 250 450 650 850 1050 i out (ma) load regulation (%) v in = 3.3v f s = 1mhz 9v 12v 0.5 -0.5 5v 15v 3 2.5 2 1 -0.5 -1 -1.5 50 250 450 650 850 1050 i out (ma) load regulation (%) v in = 5v f s = 1mhz 9v 12v 1.5 0 15v 0.5
el7581 fn7100 rev 5.00 page 6 of 17 march 9, 2006 figure 7. load regulation figure 8. load regulation figure 9. v on vs i on figure 10. v off vs i off figure 11. f s vs r osc figure 12. switching period vs r osc typical performance curves (continued) 4 3 2 0 -2 50 250 450 650 850 1050 i out (ma) load regulation (%) 9v 12v 1 15v -1 v in = 3.3v f s = 700khz 5v 3 2.5 2 1 -1 -1.5 -2 50 250 450 650 850 1050 i out (ma) load regulation (%) 9v 12v 1.5 -0.5 15v 0 v in =5v f s = 700khz 0.5 20 19 18 17 16 15 14 010 20304050 607080 i load (ma) v on (v) v ddp = 15v v ddp = 12v i load (ma) v off (-v) 6.5 6 5.5 5 4.5 4 3.5 010 20304050607080 v ddn = 15v v ddn = 12v f(mhz) = 1/(0.0118 r osc + 0.378) 1400 1000 800 400 0 0 50 100 200 450 r osc (k ? ) frequency (khz) 150 300 600 200 400 1200 250 350 switching period (s) = 0.0118 r osc + 0.378 6 4 3 1 0 0 50 100 200 450 r osc (k ? ) switching period (s) 150 300 2 400 5 250 350
el7581 fn7100 rev 5.00 page 7 of 17 march 9, 2006 figure 13. f s vs v ddb figure 14. v ref vs temperature figure 15. boost stage figure 16. v on ripple figure 17. v on ripple figure 18. v off ripple typical performance curves (continued) 970 968 966 964 962 33.5 6 v ddb (v) frequency (khz) 4.5 965 963 5.5 969 45 967 r osc = 61.9k ? ?? ?? ? ??? ? v boost (20mv/div) i o = 5ma, v on = 18v, c on = 2.2f 2s/div 50mv/div 2s/div 50mv/div i o = 18ma, v on = 18v, c on = 2.2f 10s/div 20mv/div i o = 5ma, v off = -6v, c off = 3.3f
el7581 fn7100 rev 5.00 page 8 of 17 march 9, 2006 figure 19. v off ripple figure 20. boost conver ter transient response figure 21. start-up voltage and current figure 22. start-up voltage and current figure 23. power-up, no delay rc network on enable pins figure 24. power-down, no delay rc network on enable pins typical performance curves (continued) 2s/div 20mv/div i o = 15ma, v off = -6v, c off = 3.3f 20s/div i o v boost = 13v, i o = 100ma to 420ma, c boost = 22f ? v o (100mv/div) 1ms/div v in 2v/div i in 0.5a/div c ss = 0.033f 1ma/div v in 2v/div i in 0.5a/div c ss = 0.1f v boost 100ma v on v off 5v/div 2v/div 10v/div 1ms/div c ss = 0.1f v boost v on v off 5v/div 2v/div 10v/div 200ms/div c ss = 0.1f
el7581 fn7100 rev 5.00 page 9 of 17 march 9, 2006 figure 25. power-down, 100k and 0.1f delay network on enp figure 26. power-up, 100k and 0.1f delay network on enp figure 27. lx waveform - discontinuous mode figure 28. lx waveform - continuous mode figure 29. 20-pin htssop th ermal resistance vs pcb area, no air flow figure 30. package power dissipation vs ambient temperature typical performance curves (continued) v boost v on v off 5v/div 2v/div 10v/div 200ms/div c ss = 0.1f v boost v on v off 5v/div 2v/div 10v/div 1ms/div c ss = 0.1f v in = 3.3v v out = 11.3v i out = 50ma v in = 3.3v v out = 11.3v i out = 250ma 50 45 40 35 30 25 12345678 9 pcb area (in 2 ) ? ja (c/w) condition: 20-pin htssop thermal pad soldered to 2-layer pcb with 0.039" thickness and 1-oz copper on both sides 3.5 3 2.5 1.5 1 0.5 0 0 25 50 75 100 150 ambient temperature (c) power dissipation (w) 2.857w ? j a = 3 5 c / w h t s s o p 2 0 125 85 2 jedec jesd51-7 high effective thermal conductivity test board htssop exposed diepad soldered to pcb per jesd51-5
el7581 fn7100 rev 5.00 page 10 of 17 march 9, 2006 block diagram figure 31. package power dissipation vs ambient temperature typical performance curves (continued) 1 0.9 0.6 0.4 0.3 0.2 0.1 0 0 25 50 75 100 150 ambient temperature (c) power dissipation (w) 85 0.8 0.5 0.7 125 800mw ? j a = 1 2 5 c /w h t s s o p 2 0 jedec jesd51-3 low effective thermal conductivity test board start-up oscillator - + i lout pwm logic r osc enbn fbb v ddb lx v ssb pgnd ss max_duty v ref v ramp r 2 r 1 v out 10h v in 0.15 ? 80m ? 7.2k 12a pwm comparator reference generator r 3 62k ? 0.1f 10f 10f 13k ? 110k ? 49 ? 0.1f
el7581 fn7100 rev 5.00 page 11 of 17 march 9, 2006 applications information the el7581 is high efficiency mu ltiple output power solution designed specifically for thin-f ilm transistor (tft) liquid cry stal display (lcd) applications. the device contains one high current boost converter and two low power charge pumps (v on and v off ). the boost converter contains an integrated n-channel mosfet to minimize the number of external components. the converter output voltage can b e set from 5v to 18v with external resistors. the v on and v off charge pumps are independently regulated to pos itive and negative voltages using external resistors. out put voltages as high as 40v can be achieved with additional capacitors and diodes. boost converter the boost converter operates in constant frequency pulse- width-modulation (pwm) mode. quiescent current for the el7581 is only 5ma when enabled, and since only the low side mosfet is used, switch drive current is minimized. 90% efficiency is achieved in most common application operating conditions. a functional block diagram with ty pical circuit configuration i s shown on the previous page. r egulation is performed by the pwm comparator which regul ates the outpu t voltage by comparing a divided output volt age with an internal reference voltage. the pwm comparator o utputs its result to the pwm logic. the pwm logic switch es the mosfet on and off through the gate drive circui t. its switching frequency is external adjustable with a resi stor from timing control pin (r osc ) to ground. the boost converter has 200khz to 1.2mhz operating frequency range. start-up after v ddb reaches a threshold of about 2v, the power mosfet is controlled by the start-up oscillator, which generates fixed duty-ratio of 0.5 - 0.7 at a frequency of sever al hundred kilohertz. this will boost the output voltage, providin g the initial output c urrent load is not too great (<250ma). when v ddb reaches about 3.7v, the pwm comparator takes over the control. the duty rati o will be decided by the multipl e- input direct summing comparator, max_duty signal (about 90% duty-ratio), and the current limit comparator, whichever is the smallest. the soft-start is provided by th e current limit c omparator. as the internal 12a current source charges the external soft-star t capacitor, the peak mosfet curr ent is limited by the voltage on the capacitor. this in turn co ntrols the rising rate of outp ut voltage. the regulator goes through the start-up sequence as well after the enbn signal is pulled to hi. steady-state operation when the output reaches the pr eset voltage, the regulator operates at steady state. depe nding on the input/output condition and compone nt, the inductor o perates at either continuous-conduction mode or discontinuous-conduction mode. in the continuous-conduction m ode, the inductor current is a triangular waveform and lx volt age a pulse waveform. in the discontinuous-conduction mode, the inductor current is completely dried-out before t he mosfet is turned on again. the input voltage source, the inductor, and the mosfet and output diode parasitic capacitors forms a resonant circuit. oscillation will occur in this per iod. this oscillation is norm al and will not affect the regulation. at very low load, the mosfet wi ll skip pulse sometimes. this is normal. current limit the mosfet current limit is nominal i lmt = 2.75a. this restricts the maximu m output current i omax based on the following formula: where: ? ? i l is the inductor peak-to-peak current ripple and is decided by: ? d is the mosfet turn-on radio and is decided by: ?f s is the switching frequency. the following table gives typical values: (margins are considered in deriving i omax . they are 10%, 3%, 20%, 10%, and 20% on v in , v o , l, f s , and i lmt , respectively.) table 1. maximum continuous output current v in (v) v o (v) l (h) f s (khz) i omax (ma) 3.3 5 10 1000 1200 3.3 9 10 1000 660 3.3 12 10 1000 490 3.3 15 10 1000 390 5 9 10 1000 980 5 12 10 1000 720 5 15 10 1000 570 12 15 10 1000 1300 12 18 10 1000 1100 i omax i lmt ? l 2 ------ - C ?? ?? v in v o --------- ? = ? i l v in l --------- d f s ------ - ? = - ----------------------- - =
el7581 fn7100 rev 5.00 page 12 of 17 march 9, 2006 component considerations input capacitor it is recommended that c in is larger than 10f. theoretically, the input capacitor has ripple current of ? i l . due to high- frequency noise in the circuit, the input current ripple may exceed the theoretical value. l arger capacitor will reduce the ripple further. boost inductor the inductor has peak and av erage current decided by: the inductor should be chosen to be able to handle this current. furthermore, due to the fixed internal compensation, i t is recommended that maximum i nductance of 10h and 15h to be used in the 5v and 12v or higher output voltage, respectively. the output diode has a verage current of i o , and peak current the same as the inductor's pe ak current. schottky diode is recommended and it should be ab le to handle those currents. feedback resistor network an external resistor divider is required to divide the output voltage down to the nominal reference voltage. current drawn by the resistor network should be limited to maintain the overa ll converter efficiency. the max imum value of the resistor network is limited by t he feedback input bias current and the potential for noise being coup led into the feedback pin. a resistor network i n the order of 200k ? is recommended. the boost converter output voltage i s determined by the following relationship: where v fbb is 1.300v as specified. a 3.9nf compensation capacitor across the feedback resistor to ground is recommended to k eep the converter in stable operation at low output curren t and high frequency conditions. schottky diode speed, forward voltage drop, and reverse current are the three most critical sp ecifications for selecting the schottky diode. the entire output current flows through the diode, so the diode average current is the same as the average load current and the peak current is the same a s the inductor peak current. when selecting the diode, on e must consider the forward voltage drop at the peak diode c urrent. on the elantec demo board, mbrm120 is selected. it s forward voltage drop is 450mv at 1a forward current. output capacitor the el7581 is specially com pensated to be stable with capacitors which have a worst-case minimum value of 10f at the particular v out being set. output ripple voltage requirements also determine the minimum value and the type of capacitors. output rippl e voltage consists of two components - the voltage drop caused by the switching current though the esr of the output cap acitor and the charging and discharging of the output capacitor: for low esr ceramic capacitors, the output ripple is dominated by the charging/discharging of the output capacitor. in addition to the voltage rati ng, the output capacitor should also be able to handle the rms current is given by: positive and negative charge pump (v on and v off ) the el7581 contains two ind ependent charge pumps (see charge pump block and connection diagram.) the negative charge pump inverts the v ddn supply voltage and provides a regulated negative ou tput voltage. the positive charge pump doubles the v ddp supply voltage and provides a regulated positive output voltage. the re gulation of both the negative an d positive charge pumps is generated by the internal comparator that senses the output volt age and compares it with and internal reference. the switc hing frequency of the charge pump is set to ? the boost con verter switching frequency. the pumps use pulse width m odulation to adjust the pump period, depending on the load present. the pumps are short- circuit protected to 180ma at 1 2v supply and can provide 15ma to 60ma for 6v to 12v supply. i lpk i lavg ? i l 2 -------- + = - ------------- = + r 1 -------------------- - v fbb ? = - ------------------------------- - + ? i out c out fs ? ------------------------------ ? = ? - d ? d ? i l 2 i lavg 2 ------------------- - + ? ? ? ? ? 1 12 ------ ? ? ? ? ? i lavg ? =
el7581 fn7100 rev 5.00 page 13 of 17 march 9, 2006 positive charge pump design considerations a single stage charge pump is shown above. the maximum v on output voltage is determi ned by the following equation: where: ?r onn and r onp resistance values depend on the v ddp voltage levels. for 12v supply, r on is typically 33 ? . for 6v supply, r on is typically 45 ? . if additional stage is require d, the lx switching signal is recommended to drive the additional charge pump diodes. the drive impedance at the lx s witching is typically 150m ? . the figure on the next page illustra tes an implementation for two- stage positive charge pump circuit. - + + - osc - + r 21 r 22 v ref (1.32v) 3.3f 0.1f 5v to 17v v ddn drvn v ssn v ddp drvp v ssp fbp fbn v fbp r 11 r 12 2.2f 0.1f 5v to 17v v off v on r on is 30 - 40 ? for v dd 6v to 17v r onp r onn r onp r onn c out2 c cpn c cpp c out1 v on max ?? 2v ddcpp - i out 2r onn ? r onp ? - 2 v diode - i out 1 0.5 f s c cpp ? ? ------------------------------------------- - ? ? + ? ? ? - i out 1 0.5 f s c out1 ? ? ----------------------------------------------- - ? ?
el7581 fn7100 rev 5.00 page 14 of 17 march 9, 2006 two-stage positive charge pump circuit the maximum v on output voltage for n+ 1 stage charge pump is: r 11 and r 12 set the v on output voltage: where v fpb is nominal 1.310v. negative charge pump design considerations the criteria for the negative charge pump is similar to the positive charge pump. for a sin gle stage charge pump, the maximum v off output voltage is: similar to positive charge pump, if additional stage is require d, the lx switching signal is recommended to drive the additional charge pump diodes. the figure on the next page shows a two stage negative charge pump circuit. - + + - v ssp drnp fbp 1.265v v ddp c cpp c out1 v boost (5v-17v) v lx c out1 r 12 r 11 c cpp v on r onp r onn v on max ?? 2v ddp - i out 2r onn ? r onp ? - 2 v diode - i out 1 0.5 f s c cpp ? ? -------------------------------------------- ? ? + ? ? ? - i out 1 0.5 f s c out1 ? ? ----------------------------------------------- - ? nv lx max ?? - n 2 v diode i out 1 0.5 f s c cpp ? ? -------------------------------------------- ? + ? ? ? ? ? i out 1 0.5 f s c out1 ? ? ----------------------------------------------- - ? ? ? ++ ? + r 11 -------------------------- - ? = ?? i out 2r onn ? r onp ? 2v diode - i out 1 0.5 f s c cpn ? ? -------------------------------------------- ? ? ++ ? ? - i out 1 0.5 f s c out2 ? ? ----------------------------------------------- - ? - v ddn ?
el7581 fn7100 rev 5.00 page 15 of 17 march 9, 2006 two-stage negative charge pump circuit the maximum v off output voltage for n+1 stage charge pump is: r 21 and r 22 determine v off output voltage: where v ref is nominal 1.310v. over-temperature protection an internal temperature sensor continuously monitors the die temperature. in the event that die temperature exceeds the thermal trip point, the device wil l shut down and disable itsel f. the upper and lower trip points are typically set to 130c and 90c respectively. pcb layout guidelines careful layout is critical in the successful operation of the application. the following layout guidelines are recommended to achieve optimum performance. ?v ref and v ddb bypass capacitors should be placed next to the pins. ? place the boost converter diode and inductor close to the lx pins. ? place the boost converter ou tput capacitor close to the pgnd pins. ? locate feedback dividers close to their respected feedback pins to avoid switching no ise coupling into the high impedance node. ? place the charge pump feedback resistor network after the diode and output cap acitor node to avoid switching noise. ? thermal pad needs to be c onnected to pgnd pins electrically, and it should be soldered to pcb with thermal vias connecting to ground plane for maximum heat dissipation. ? all low-side feedback resistors should be connected directly to v ssb . v ssb should be connected to the power ground close at one point only. a demo board is available to illustrate the proper layout implementation. - + v ssn drvn fbn v ddn c cpn c out2 v lx c out2 r 21 r 22 c cpn v ref v off 5v-17v r onn r onp v off max ?? i out 2r onn ? r onp ? 2v diode - i out 1 0.5 f s c cpn ? ? -------------------------------------------- ? ? ++ ? ? - i out 1 0.5 f s c out2 ? ? ----------------------------------------------- - - v ddn ? - n v lx max ?? n2v diode i out 1 0.5 f s c cpn ? ? -------------------------------------------- ? + ? ? ? ? + ? i out 1 0.5 f s c out2 ? ? ----------------------------------------------- - ? ? ? + ? C ref r 21 r 22 --------- - ? =
el7581 fn7100 rev 5.00 page 16 of 17 march 9, 2006 typical application circuit * mbrm120lt3 ** bat54s 0.1f 0.1f c 11 c 12 r 11 3.9k r 12 51k c 16 0.1f c 17 2.2f v on (18v@18ma) l1 10h d1* r 4 49.9 c 6 0.1f c 22 0.1f c 21 0.1f d 21 ** r 21 154k c 26 3.3f c 27 0.1f r 22 33.2k v off (-6v@ 15ma) r 3 61.9k r 5 499k r 6 0 c 8 0.1f c 50 open c 3 22f c 4 open c 5 10f c 9 1nf c 10 open d 11 ** r 1 13k r 2 110k v boost (12v@ 500ma) c 2 4.7f c 1 10f v in gnd c 7 0.1f 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 + + rosc enp enbn vref pgnd pgnd drvp vddp fbp vssp vssb ss fbb vddb lx lx lx drvn vddn fbn
fn7100 rev 5.00 page 17 of 17 march 9, 2006 el7581 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2004-2006. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. package outline drawing note: the package drawing shown here may not be the latest versi on. to check the latest revision , please refer to the intersil website at http://www.intersil.com/design/packages/index.asp

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